ESE Ph.D. Thesis Defense – “Accelerating HLS Autotuning of Large, Highly-Parameterized Reconfigurable SoC Mappings”

High-level synthesis has accelerated the adoption of autotuners to explore design spaces. Design-space size increases exponentially in the number of design parameters, and synthesizing a single configuration for a device-scale application easily consumes hours, so existing autotuners are frequently demonstrated with small kernels and few configurations to render the problem tractable. This dissertation shows that exploration of applications with more than 25 parameters mapped on reconfigurable SoCs exceeding 200K LUTs becomes feasible using the model-based approach we refine. We explore various techniques to reduce the tuning time. At the heart of our tuner are multi-fidelity models, which enable discontinuation of unpromising builds in multi-stage CAD flows. We rearranged the build resources in a pipeline to improve the tuning performance and increase the utilization of build resources. Build failures and underperforming configurations are avoided using latency, area, critical path delay, congestion, error probability, and build time prediction models. Next, we introduce a novel model that combines the preexisting hierarchical and multi-fidelity models. The hierarchical model enables the decomposition of design spaces into exponentially smaller subspaces that can be explored faster. Also novel is the use of out-of-context compilation to lower the build time further. A tree-based model alleviates the long training times of Gaussian process models. To validate our approach, we injected 29 – 44 parameters, varying from compiler pragmas to CAD tool parameters, in the Rosetta benchmarks. Compared to non-pipelined multi-fidelity Bayesian optimization, our tuner succeeds 20% more often at finding mappings on the ZCU102, and tuning runs are on average at least 2.2x shorter. Moreover, it locates 3.6x faster solutions within 24 hours.