ESE PhD Thesis Defense: “Software-like Incremental Refinement on FPGA using Partial Reconfiguration”

To improve FPGA design productivity, our goal is to create a development experience for FPGAs that aligns closely with widely accepted software design principles. Software programmers quickly test their minimally completed design, identify the bottleneck, and incrementally refine the design. In FPGA design, however, such incremental refinement is not currently supported. (1) FPGA compilation is long, (2) a minor refinement leads to another long compilation, and (3) FPGA developers cannot easily identify a bottleneck of the design to know where to focus optimization effort to improve the application execution time. We introduce a divide-and-conquer strategy in FPGA compilation, proposing a fast separate FPGA compilation using a Network-on-Chip (NoC) and Partial Reconfiguration (PR). Building upon this separate compilation framework, in this thesis, we take the next step to support variable-sized pages using Hierarchical PR to provide flexibility to the users. With variable-sized pages, users can quickly test the design on the hardware, just like software programmers start from a barely functional design. In addition, we propose a bottleneck identification scheme based on FIFO counters to provide profiling capability in FPGA design. Finally, we introduce a fast incremental refinement strategy that integrates our fast compilation framework and bottleneck identification scheme. The idea is to quickly map the design on the FPGA using the fast compilation framework and incrementally refine the design based on our bottleneck identification. The fast compilation with the NoC and PR pages iterates many initial yet important design points quickly, and for the final, optimized design, our strategy migrates to the monolithic system that does not have the area and bandwidth overhead of the NoC. Throughout the design tuning, we always have a hardware-mapped design whose performance we can measure to provide feedback to the users or automation script to identify the next bottleneck. We evaluate our fast incremental strategy with design tuning for realistic High Level Synthesis applications. Our framework, fully compatible with AMD Vitis, achieves 1.3–2.7× faster tuning time than a monolithic flow where the vendor tool monolithically compiles each design point.