ESE PhD Thesis Defense: “Accelerating FPGA Developments from C to Bitstreams by Partial Reconfiguration”

Divide-and-Conquer and incremental compilation strategies are widely used in software compilations. To enable these strategies for FPGAs, this dissertation presents an open-source framework called PRflow, which can speed up the compilation times by at most an order of magnitude. PRflow supports different optimization levels to make better trade-offs among compile-time, area, and performance. -O0 (PRflow_RISCV) maps applications to a cluster of on-chip RISC-V cores within seconds for quick verification and debugging. -O1 (PRflow) compiles the separate parts of an application to partial FPGA bitstreams for different Partial reconfigurable regions on the chip. Individual parts can be compiled in parallel within 24 minutes. The interconnections between separate parts can be recompiled by configuring the NoC by sending configuration packets by the host. -O2 (PRflow_DW) supports inter-connection customization with a fixed page-size overlay on top of commercial FPGA to meet high inter-page bandwidth requirements which can improve the performance by up to 10X compared with -O1. -O3 (PRflow_HiPR) supports overlay customization for higher inter-page throughput and various size requirements with similar incremental compile time to -O1 and -O2. This dissertation demonstrates the PRflow framework on the Xilinx Alveo-U50 data-center card with an xcu50-fsvh2104-2-e FPGA chip (14nm FinFET) by mapping Rosetta HLS complete benchmark set. PRflow can accelerate the compilation times from 2–3 hours (state-of-art Vitis) to 10-24 minutes.