ESE Fall Seminar – “Beyond the Exit of the Device Miniaturization Tunnel”
September 23 at 11:00 AM - 12:00 PM
For the past fifty years, researchers of semiconductor technology have felt like walking inside a tunnel. There was a single path forward – two-dimensional down-scaling of device sizes, also referred to as 2D miniaturization. With device features approaching atomic scale, semiconductor technology has reached the exit of this tunnel. The future is bright at the exit of the tunnel as there are many possible paths that create new opportunities for architectures that are extremely difficult (or even impossible) to implement using existing technology approaches that rely mainly on 2D miniaturization. It is no longer possible to draw a clear boundary between design and fabrication. Many innovations across the entire system stack – from architectures to circuits, devices, fabrication processes, and materials – will provide large multiplicative benefits at the system level. And there will be a change in the supplier-integrator and fabless-foundry ecosystems that have been in place for over 30 years.
Specifically, AI computation benefits tremendously simply by having more on-chip memory capacity. To derive the highest energy efficiency, not only the chip architecture needs to be application domain specific, but the memory technologies must also be application domain-specific to capture the highest benefits while incurring the lowest impact on latency, bandwidth and cost. As an example, I will describe the use of ultra-low leakage transistors (< 10-18 A/µm) with large band gap oxide semiconductor materials to build gain cell memory. Gain cell memory has only two transistors and can be built in a 3D stack (thus small cell size and high density) that can complement SRAM to provide larger on-chip memory capacity [1]. More importantly, these memory technologies can be integrated on Si logic chips to arrive at a computing system that integrates multiple heterogeneous device technologies in a 3D monolithic, stacked, assembled integrated circuit: 3D MOSAIC [2]. These Differentiated Access Memory (DAM) systems will require us to revisit and re-examine computing at all levels, from the design of new memory technologies to high-level algorithms.
[1] S. Liu et al., “Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development,” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413726.
[2] R. M. Radway et al., “The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design,” 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 25.4.1-25.4.4, doi: 10.1109/IEDM19574.2021.9720647.
Acknowledgements: This presentation benefits from a long-time collaboration with Prof. Subhasish Mitra (Stanford). This work is supported in part by Department of Defense Microelectronics Commons California-Pacific-Northwest AI Hardware Hub, Eccalon/DoD, National Science Foundation (award number 2235329), SRC JUMP 2.0 CHIMES Center and PRISM Center, and member companies of the Stanford SystemX Alliance, Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and the Stanford Differentiated Access Memory (DAM) industry affiliate programs.
H.-S. Philip Wong
Willard R. and Inez Kerr Bell Professor of Electrical Engineering, Stanford University
H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University. He joined Stanford University as Professor of Electrical Engineering in 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center. From 2018 to 2020, he was on leave from Stanford and was the Vice President of Corporate Research at TSMC, the largest semiconductor foundry in the world, and since 2020 remains the Chief Scientist of TSMC in a consulting, advisory role. He is a Fellow of the IEEE and received the IEEE Andrew S. Grove Award, the IEEE Technical Field Award to honor individuals for outstanding contributions to solid-state devices and technology, as well as the IEEE Electron Devices Society J.J. Ebers Award, the society’s highest honor to recognize outstanding technical contributions to the field of electron devices that have made a lasting impact. He is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems and served as the faculty director of the Stanford Nanofabrication Facility – a shared facility for device fabrication on the Stanford campus that serves academic, industrial, and governmental researchers across the U.S. and around the globe, sponsored in part by the National Science Foundation. He is the Principal Investigator of the Microelectronics Commons California-Pacific-Northwest AI Hardware Hub, a consortium of over 40 companies and academic institutions funded by the CHIPS Act. He is a member of the US Department of Commerce Industrial Advisory Committee on microelectronics.