ESE PhD Thesis Defense: “Software-like Incremental Refinement on FPGA using Partial Reconfiguration”
Raisler Lounge (Room 225), Towne Building 220 South 33rd Street, PhiladelphiaTo improve FPGA design productivity, our goal is to create a development experience for FPGAs that aligns closely with widely accepted software design principles. Software programmers quickly test their minimally completed […]