This talk will discuss the opportunities and progress for AI models and hardware accelerator co-design towards the goal of efficient general intelligence (EGI). Some successful examples include hierarchical memory transformer (HMT), lookup-table (LUT) based large-language models (LLMs) and customized acceleration of the LLM memory-processing pipeline.

The talk will also present the latest research results at UCLA on using AI/ML techniques, such as graph neural networks (GNNs), LLMs and agentic approaches, coupled with algorithmic methods, such as high-level synthesis and non-linear programming, to automate chip designs to enable rapid design of deep learning models on customized silicon.