The Harold Pender Award Lecture
March 18 at 2:00 PM - 3:00 PM
This talk will discuss the opportunities and progress for AI models and hardware accelerator co-design towards the goal of efficient general intelligence (EGI). Some successful examples include hierarchical memory transformer (HMT), lookup-table (LUT) based large-language models (LLMs) and customized acceleration of the LLM memory-processing pipeline.
The talk will also present the latest research results at UCLA on using AI/ML techniques, such as graph neural networks (GNNs), LLMs and agentic approaches, coupled with algorithmic methods, such as high-level synthesis and non-linear programming, to automate chip designs to enable rapid design of deep learning models on customized silicon.
Jason Cong
Jason Cong, UCLA Volgenau Chair for Engineering Excellence | Computer Science, Electrical and Computer Engineering
Jason Cong is the Volgenau Chair for Engineering Excellence in the UCLA Computer Science Department, with a joint appointment in Electrical and Computer Engineering. He directs UCLA’s Center for Domain-Specific Computing and the VLSI Architecture, Synthesis and Technology (VAST) Laboratory.
A member of the National Academy of Engineering and a Fellow of the IEEE, ACM and the National Academy of Inventors, Cong is widely recognized for foundational contributions to electronic design automation, FPGA synthesis and customizable computing. His work has shaped both academic research and commercial technologies across the semiconductor industry.