ESE Ph.D. Thesis Defense – “Accelerating HLS Autotuning of Large, Highly-Parameterized Reconfigurable SoC Mappings”
Room 35, Singh Center for Nanotechnology 3205 Walnut Street, Philadelphia, PAHigh-level synthesis has accelerated the adoption of autotuners to explore design spaces. Design-space size increases exponentially in the number of design parameters, and synthesizing a single configuration for a device-scale application easily consumes hours, so existing autotuners are frequently demonstrated with small kernels and few configurations to render the problem tractable. This dissertation shows that […]